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6-ch, 4.5-V to 5.5-V inverters with TTL-compatible CMOS inputs
Data sheet
- document-pdfAcrobat CD54HCT04, CD74HCT04 High-Speed CMOS Logic Hex Inverter datasheet
CD74HCT04
Product details
- LSTTL input logic compatible
- VIL(max) = 0.8 V, VIH(min) = 2 V
- CMOS input logic compatible
- II ≤ 1 µA at VOL, VOH
- Buffered inputs
- 4.5 V to 5.5 V operation
- Wide operating temperature range: -55°Cto+125°C
- Supports fanout up to 10 LSTTL loads
- Significant power reduction compared to LSTTL logic ICs
- LSTTL input logic compatible
- VIL(max) = 0.8 V, VIH(min) = 2 V
- CMOS input logic compatible
- II ≤ 1 µA at VOL, VOH
- Buffered inputs
- 4.5 V to 5.5 V operation
- Wide operating temperature range: -55°Cto+125°C
- Supports fanout up to 10 LSTTL loads
- Significant power reduction compared to LSTTL logic ICs
This device contains six independent inverters. Each gate performs the Boolean function Y= A in positive logic.
This device contains six independent inverters. Each gate performs the Boolean function Y= A in positive logic.
Technical documentation
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View all 12| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | CD54HCT04, CD74HCT04 High-Speed CMOS Logic Hex Inverter datasheet | 29 Aug 2019 | |
| Application note | Implications of Slow or Floating CMOS Inputs (Rev. E) | 26 Jul 2021 | ||
| Selection guide | Logic Guide (Rev. AB) | 12 Jun 2017 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 02 Dec 2015 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 16 Jan 2007 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 08 Jul 2004 | ||
| User guide | Signal Switch Data Book (Rev. A) | 14 Nov 2003 | ||
| Application note | TI IBIS File Creation, Validation, and Distribution Processes | 29 Aug 2002 | ||
| Application note | CMOS Power Consumption and CPD Calculation (Rev. B) | 01 Jun 1997 | ||
| Application note | Designing With Logic (Rev. C) | 01 Jun 1997 | ||
| Application note | SN54/74HCT CMOS Logic Family Applications and Restrictions | 01 May 1996 | ||
| Application note | Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc | 01 Apr 1996 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.
Evaluation board
14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages
The 14-24-LOGIC-EVM evaluation module(EVM)is designed to support any logic device that is in a 14-pin to 24-pinD, DW, DB, NS, PW, DYYor DGV package,
User guide: PDF | HTML
Not available on TI.com
Simulation model
CD74HCT04 Behavioral SPICE Model
SCHM095.ZIP (7 KB) - PSpice Model
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| PDIP (N) | 14 | Ultra Librarian |
| SOIC (D) | 14 | Ultra Librarian |
| TSSOP (PW) | 14 | Ultra Librarian |
TI's Standard Terms and Conditions for Evaluation Items apply.
Ordering & quality
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Learn more
Information included:
- RoHS
- REACH
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- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
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Information included:
- Fab location
- Assembly location
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